搜索资源列表
Serial_Adder
- 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver
32bit_add_exercise
- 32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助-32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译，并使用modelsim进行了验证，内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
Combinational
- this is a sample of combinational circuit in Verilog and VHDL. such as multiplexer, decoder, adder etc
pre_counter
- 超前进位加法器，硬件实现，FPGA,verilog-Carry lookahead adder, hardware implementation, FPGA
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
add8
- 8*8位全加器的代码 verilog语言，包含测试文件(8*8-bit full adder code verilog)
超前进位加法器
- 8*8超前进位加法器，Verilog初学教程(file name is adder.v adder 8*8 bit)
add_1p
- 用于FPGA的加法器实现程序，采用Verilog语言编写(Adder implementation program for FPGA)
add_2p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用了两级流水线方法(Adder implementation program for FPGA)
add_3p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用三级流水线方法(Adder implementation program for FPGA)
RippleCarryAdderHW
- it is ripplecarry adder example in verilog
编写一个4比特加法器
- 用Verilog编程实现一个4bit加法器(Write a program to implement a 4 bit-adder.)